In the prior art, a nonvolatile memory array usually consists of a plurality of memory cells aligned in rows and columns, with each memory cell having one or more transistors. Various strategies have been employed to build multibit cells, with a typical requirement that there be two floating elements that can be controlled independently. For example, in prior application Ser. No. 10/4423,637 entitled, “Mirror Image Memory Cell Transistor Fairs Featuring Poly-Floating Spacers”, assigned to the assignee of the present invention, B. Lojek described an arrangement of nonvolatile MOS memory transistors for memory array wherein symmetric pairs of transistors shared a drain electrode in a common well, but were otherwise completely independent. The pair was manufactured between a pair of isolation regions and so shared the same substrate region, almost as if a single transistor were constructed there. A different approach was employed in prior application Ser. No. 10/427,336 entitled, “Multi-Level Memory Cell with Lateral Floating Spacers”, assigned to the assignee of the present invention. In this instance, a single MOS floating gate transistor stored two data bits using two spacers, on opposite sides of the conductive gate. The spacers behave as independent charge storage regions for separate binary data, thereby allowing a single nonvolatile MOS transistor to store two binary bits. Each memory cell was connected to two bit lines and one word line. The bit lines are phased so that during a single clock cycle, first one bit line is active and then the other while a word line is active for the entire cycle. In this manner, both storage areas may be accessed for a read or a write operation.
One of the limits to compactness of the memory array is set by contacts to transistor electrodes. In the prior art, contactless geometries have been devised that reduce the number of transistor contacts to single lines that communicate with electrodes in each cell. This is done by building memory arrays with a stripe geometry, with stripes running in both X and Y directions. The stripes are either conductors above the surface of a wafer substrate or doped conductive regions in the substrate, or both. The stripes form lines which run through individual cells in a manner that allows addressing for writing, erasing, and reading. For example, see U.S. Pat. No. 7,061,801 to Wang.
Once this level of compactness has been achieved, an object of the invention is to achieved are used.